Design of High Speed Vedic Square by using Vedic Multiplication Techniques

Digital signal processors (DSPs) are very important in various engineering disciplines. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transforms, digital filters,etc. As in all the arithmetic operations, it is the squaring which is most important in finding the transforms or the inverse transforms in signal processing. The squaring operation occupies most of the computing time, therefore it is necessary to concentrate on the improvement of speed with which. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. This is a highly modular design in which smaller blocks can be used to build higher blocks. Vedic square is designed by using Verilog HDL coding and compared the performance with the modified Wallace tree in terms of time delay and area occupied on the Xilinx Spartan xc3s500e-5fg320.